• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Disclosed is a semiconductor device and a method for manufacturing the same, which greatly reduce the height of a step between a first resist trace for forming a wiring pattern in a product region and a second resist trace for forming an accessory pattern such as an alignment mark. It is about. The second resist trace is formed on the protrusion. The protruding portions are intentionally left and insulated and conductive layers corresponding to the first and second interlayer insulating films, the storage electrodes and the plate electrodes formed on the wiring pattern in the product region, and the second upper layer of the conventional apparatus. It consists of a wiring and a base film. By greatly reducing the height of the step between the two wirings, it is possible to improve the focus control between the two patterns, and to form the shapes of the resist with high precision.
    公开号:KR19990036785A
    申请号:KR1019980041448
    申请日:1998-10-01
    公开日:1999-05-25
    发明作者:마사테루 안도
    申请人:가네꼬 히사시；닛본 덴기 가부시끼가이샤；
    IPC主号:
    专利说明:

    Semiconductor device and manufacturing method
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly, to a method for manufacturing accessory pattern structures such as alignment marks and accessory pattern structures in a semiconductor device.
    In recent years, with the high integration of LSI, the device area decreases every year, and improving the accuracy of alignment while maintaining high yield has become one of the important factors in the production of semiconductor devices. As one factor that greatly influences the accuracy of alignment, there is visibility of alignment marks, and an excellent resist shape must be secured for this purpose.
    1 to 4 show a conventional method for manufacturing alignment marks in a semiconductor device such as a DRAM using a stacked capacitor structure. In Fig. 1, reference numeral 1 denotes a semiconductor substrate made of P-type silicon or the like. On the non-active area of the semiconductor substrate 1, a field oxide film for element isolation is generally formed, and on the active area, for example, a word line and an N-type diffusion layer made of, for example, a first polycrystalline silicon layer. This is formed sequentially.
    Next, a first interlayer insulating film such as a SiO 2 layer, a BPSG layer, or the like is deposited on the entire surface of the semiconductor substrate 1, and a contact is provided for connecting a bit line made of a second polycrystalline silicon layer and an N-type diffusion layer. . Then, a bit line made of the second polysilicon layer is formed. Further, after the second interlayer insulating film is deposited to cover the entire surface on the semiconductor substrate 1, the contact for connecting the storage electrode 3 of the stacked capacitor structure made of the third polysilicon layer to the N-type diffusion layer. Is formed. Here, the first interlayer insulating film and the second interlayer insulating film deposited before the storage electrode 3 is formed form the interlayer insulating film 2.
    Next, the storage electrode 3 of the stacked capacitor structure made of the third polysilicon layer and the plate electrode 4 made of the fourth polycrystalline silicon layer are sequentially formed, followed by a third of a relatively thick form. The interlayer insulating film 5 is deposited. At this time, in order to reduce the step difference generated between the cell region and the peripheral circuit region by the formation of the storage electrode 3, the third interlayer insulating film 5 is, for example, conventional CMP (chemical mechanical Flattening by polishing). In addition, the scribe line region 6 is formed using conventional photolithography techniques and etching techniques. At this time, the total thickness of the film on the semiconductor substrate 1 is about 2000 nm, for example.
    In FIG. 2, the first upper layer wiring 7 such as W, AL, etc. is formed on the third interlayer insulating film 5, and then, for example, to cover the first upper layer wiring 7, for example, a plasma. A metal interlayer film 8a made of -SiO 2 is deposited. Next, a contact (through hole) for coupling the first upper wiring 7 and the second upper wiring 9 (see Fig. 3) is formed. At the same time, the base film 8b made of the plasma-SiO 2 metal interlayer film 8a is formed under the region for forming the alignment mark of the second upper layer wiring process in the subsequent process. Is formed on
    In FIG. 3, after the second upper wiring layer 9 such as W and AL is deposited, a photoresist film 10 is applied to cover the entire surface.
    Finally, in Fig. 4, the photoresist film 10 is patterned using a conventional photolithography technique to form a wiring trace of the second upper layer wiring 9 in the product region. A first resist trace 10a and a second resist trace 10b for forming alignment marks are formed. At this point, a height difference of about 2200 to 2400 nm is generated between the first and second resist traces 10a and 10b.
    For this reason, when the photolithography technique is used, the focal length of the first resist trace 10a for the wiring trace in the product region is different from the focal length of the second resist trace 10b for the alignment mart. Therefore, the resist shape of the second resist trace 10b for forming the alignment mark is extremely deteriorated, causing many problems such as a decrease in the yield, and the resist of accessory patterns such as alignment marks is not retained. When etching the upper layer wiring 9 of 2, pattern separation occurs and a yield fall is caused.
    The first problem is that when the alignment mark and the accessory pattern of the second upper layer wiring process are formed, the alignment mark and the accessory pattern are not well formed, thereby lowering the accuracy of the alignment.
    The reason for this is as follows. That is, with high integration of the device, the total layer of layers becomes thick, and the first pattern of the second upper layer wiring process in the product area and the second pattern such as alignment marks formed at a position lower than the first pattern. There is a big step in between. Therefore, in the case of using the conventional photolithography technique, the focal lengths of these two patterns are different, and it is difficult to form alignment and accessory patterns with high precision (having excellent resist shape) in the second upper wiring process. Because.
    The second problem is that in the etching step after the formation of the alignment mark and the accessory pattern in the second upper layer wiring step, pattern separation of the alignment mark and the accessory pattern portion is caused to cause yield degradation.
    The reason for this is as follows. That is, in the case of using the conventional photolithography technique, there is a large step between the first pattern of the second upper layer wiring process in the product region and the accessory pattern formed at a lower position than the first pattern. The focal lengths of the first and second resist patterns are different. This is because the resist shape of an accessory pattern such as an alignment mark is extremely deteriorated, and these resists cannot be held so that pattern separation occurs in the etching process.
    SUMMARY OF THE INVENTION The object of the present invention is to improve the accuracy of alignment without increasing the number of processes, in view of the problems of the prior art mentioned above, and to prevent the separation of the pattern from the alignment mark portion or the like, thereby preventing the degradation of the yield. The present invention provides a semiconductor device.
    It is still another object of the present invention to provide a semiconductor device manufacturing method which can improve the accuracy of alignment without increasing the number of steps, and prevents the degradation of the yield by preventing the pattern from being separated from the alignment mark portion or the like. It is.
    1 to 4 are schematic cross-sectional views sequentially showing a conventional method for manufacturing a semiconductor device.
    4 shows the final process of the method,
    5 is a schematic cross sectional view showing a method of manufacturing a semiconductor device according to the present invention in succession.
    9 shows the final process of the method.
    According to one particular aspect of the present invention, there is provided a semiconductor device comprising a protrusion formed on a substrate to form a substrate and an accessory pattern.
    According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the step of forming a protrusion on a substrate for forming an accessory pattern.
    In the present invention, the protrusion may include a plurality of insulating layers or a plurality of conductive layers. The plurality of insulating layers or conductive layers of the protrusion may correspond to the plurality of insulating layers or conductive layers provided in the pattern portion in the product region on the substrate.
    In the present invention, the protrusion forming process includes processes for forming a plurality of insulating layers or conductive layers. These plurality of insulating layers or conductive layers remain in the process for forming the plurality of insulating layers or conductive layers of the pattern portion in the product region on the substrate.
    In addition, the accessory pattern may include an alignment mark of the upper layer wiring process.
    According to the present invention, a high step between the wiring pattern and the accessory pattern can be greatly reduced. Therefore, the accuracy of alignment in the upper layer wiring process can be improved without increasing the number of steps in the conventional manufacturing process. In addition, it is possible to prevent the separation of the alignment marks from the pattern and the accessory pattern from the surface thereof, thereby preventing the degradation of the yield.
    The objects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.
    Referring to the drawings, FIGS. 5 to 9 continuously illustrate a method of manufacturing a semiconductor device such as a DRAM having a stacked capacitor structure. 9 shows a final process of the present production method.
    First, in FIG. 5, a field oxide film having a thickness of about 400 nm is selectively formed on the P-type silicon semiconductor substrate 1 by the LOCOS method to partition the active region. On this active region, a gate oxide film having a thickness of about 15 nm is formed by thermal oxidation. Subsequently, a first polysilicon layer having a thickness of about 200 nm is deposited on the gate oxide film, and this surface is patterned using a conventional photolithography technique to form a gate electrode. Then, using the field oxide film and the gate electrode as a mask, impurities such as phosphorous are implanted into the semiconductor substrate 1 to form an N-type diffusion layer (LDD region) on the surface thereof.
    Then, a first interlayer insulating film such as a SiO 2 layer, a BPSG, or the like is deposited on the entire surface of the semiconductor substrate 1, and a contact for connecting the bit line made of the second polysilicon layer and the N-type diffusion layer is connected to a conventional photoelectric film. It is formed using a lithography technique and dry etching (anisotropic) technique. Then, the bit lines of the second polysilicon layer are formed. Subsequently, a second interlayer insulating film is further deposited to cover the entire surface of the semiconductor substrate 1, and then the storage electrode of the stacked capacitor structure (see FIGS. 6 to 9) and the N-type of the third polycrystalline silicon layer is formed. A contact for connecting the diffusion layer is formed. Here, the first interlayer insulating film and the second interlayer insulating film deposited before forming the storage electrode 3 constitute the interlayer insulating film 2 having a thickness of about 600 to 700 nm.
    Next, in FIG. 6, a third polycrystalline silicon layer having a thickness of about 600 to 800 nm, which constitutes the storage electrode 3 of the stacked capacitor structure, and about 200 nm, which constitutes the plate electrode 4. Fourth polysilicon layers each having a thickness of 5 m are deposited on the front surface of the semiconductor substrate 1, and the storage electrode 3 and the plate electrode 4 are sequentially formed using conventional photolithography and etching techniques. do. At this time, the fourth polycrystalline silicon layer constituting the storage electrode 3 and the fourth electrode constituting the plate electrode 4 under the region where the alignment mark of the second upper layer wiring process formed in a subsequent process are provided. A portion of the polysilicon layer of is intentionally left on the interlayer insulating film 2.
    Next, a third interlayer insulating film 5 having a relatively thick thickness of about 1500 nm is deposited on the entire surface. Subsequently, in order to reduce the step difference generated between the cell region and the peripheral circuit region by the formation of the storage electrode 3, for example, using a conventional CMP (chemical mechanical polishing) technique or the like, it is about 300 nm. A degree of polishing is performed on the surface to flatten it. Alternatively, flattening may be performed by, for example, etching back using (63) BHF or the like.
    In Fig. 7, a contact line for connecting the first upper layer wiring 7, such as W and AL, and the N-type diffusion layer, and the striation line region 6 are formed using conventional photolithography and etching techniques. do. At this time, the fourth polycrystalline silicon layer for the plate electrode 4 serves as a mask at the time of etching, and under the region where the alignment mark of the second upper layer wiring step is provided in the later step, the storage electrode 3 A portion of the third polycrystalline silicon layer and the interlayer insulating film 2 for the purpose can be left.
    Next, after forming the first upper layer wiring 7 such as W and AL having a thickness of about 400 to 500 nm on the third interlayer insulating film 5, the first upper layer wiring 7 is formed. In order to cover this, for example, a metal interlayer film 8a made of plasma-SiO 2 having a thickness of about 500 nm is deposited. Then, a contact (through hole) for connecting the first upper wiring 7 and the second upper wiring 9 (see Fig. 8) is formed, and at the same time, the second upper wiring process is performed in a later step. Under the region where the alignment mark is provided, an underlayer 8b made of the plasma-SiO 2 metal interlayer 8a is deposited.
    In Fig. 8, the second upper layer wiring 9 such as W and AL having a thickness of about 800 to 900 nm is deposited on the entire surface by a conventional sputtering method, and then the photoresist film ( 10) Apply.
    Finally, in FIG. 9, the photoresist film 10 is patterned using a conventional photolithography technique to form a first resist trace for forming a wiring trace of the second upper layer wiring 9 in the product region. 10a) and a second resist trace 10b for forming accessory patterns such as alignment marks. In this embodiment, the height of the step between the first resist trace 10a in the product region and the second resist trace 10b constituting the alignment mark is about 500 to 700 nm, which is about 2200 to 2400 nm. Compared with the conventional case of about 1500-1700 nm degree is reduced significantly.
    In the present embodiment, as described above, the step height between the wiring pattern in the product region and the accessory pattern such as the alignment mark can be greatly reduced, thereby eliminating the problem caused by the difference in focus length between the two patterns. Therefore, the resist shape of the second resist trace 10b for forming the alignment mark can be formed with high precision, and as a result, the accuracy of alignment is improved and the excellent resist shape of accessory patterns such as alignment marks can be held. Thus, pattern separation can be prevented.
    As described above, in the present invention, the second resist trace 10b for forming accessory patterns such as alignment marks is formed on the stacked protrusions 11 deposited on the semiconductor substrate. The protrusion 11 includes an insulating layer and a conductive layer corresponding to the conventional base film 8b and the second upper layer wiring 9, the interlayer insulating film 2, the storage electrode 3, and the plate electrode of the present invention. It consists of insulating layers and conductive layers corresponding to (4).
    Although the invention has been described with reference to specific exemplary embodiments, the invention is limited only by the appended claims and not by such embodiments. It is clear that those skilled in the art can modify or change the present embodiment without departing from the spirit and spirit of the invention.
    According to the present invention, the following advantages can be achieved.
    First, the accuracy of alignment in the upper layer wiring process can be improved without increasing the number of conventional processes.
    The reason for this is as follows. That is, an accessory pattern such as an alignment mark in the upper layer wiring process, for example, an interlayer insulating film composed of, for example, polycrystalline silicon layers and, for example, an SiO 2 layer and a BPSG layer, is intentionally formed on the semiconductor substrate 1. It is because it can form on the protruding part formed by making it remain. Therefore, an accessory pattern such as an alignment mark can be formed at a position not lower than the wiring pattern in the product area, and the step difference between the wiring pattern and the accessory pattern can be greatly reduced.
    Secondly, at the time of etching the upper layer wiring process, it is possible to prevent the separation of the alignment mark and the separation of the accessory pattern from the surface, thereby preventing the degradation of the yield due to the short circuit due to the separation of the pattern.
    The reason for this is as follows. In other words, it is possible to greatly reduce the step difference between the wiring pattern of the upper layer wiring process in the product region and accessory patterns such as alignment marks generally formed at lower positions. Therefore, extreme deterioration of the resist shape of accessory patterns such as alignment marks can be effectively prevented, and a resist shape with high precision can be obtained.
    权利要求:
    Claims (12)
    [1" claim-type="Currently amended] And a protrusion formed on the substrate to form a substrate and an accessory pattern.
    [2" claim-type="Currently amended] The semiconductor device of claim 1, wherein the protrusion includes a plurality of insulating layers.
    [3" claim-type="Currently amended] The semiconductor device according to claim 1, wherein the protrusion includes a plurality of conductive layers.
    [4" claim-type="Currently amended] The semiconductor device according to claim 2, wherein the plurality of insulating layers of the protruding portion correspond to the plurality of insulating layers formed in the pattern portion in the product region on the substrate.
    [5" claim-type="Currently amended] 4. The semiconductor device according to claim 3, wherein the plurality of conductive layers of the protruding portion correspond to the plurality of conductive layers formed in the pattern portion in the product region on the substrate.
    [6" claim-type="Currently amended] The semiconductor device according to claim 1, wherein said accessory pattern includes alignment marks in an upper layer wiring process.
    [7" claim-type="Currently amended] A method of manufacturing a semiconductor device, comprising the step of forming a protrusion forming an accessory pattern on a substrate.
    [8" claim-type="Currently amended] The method of manufacturing a semiconductor device according to claim 7, wherein said protrusion forming step includes steps of forming a plurality of insulating layers.
    [9" claim-type="Currently amended] The method of manufacturing a semiconductor device according to claim 7, wherein said protrusion forming step includes steps of forming a plurality of conductive layers.
    [10" claim-type="Currently amended] The method of manufacturing a semiconductor device according to claim 8, wherein said plurality of insulating layers remain in the process of forming a plurality of insulating layers in a pattern portion in a product region on said substrate.
    [11" claim-type="Currently amended] 10. The manufacturing method of a semiconductor device according to claim 9, wherein said plurality of conductive layers remain in the process of forming a plurality of conductive layers in a pattern portion in a product region on said substrate.
    [12" claim-type="Currently amended] 8. The method of manufacturing a semiconductor device according to claim 7, wherein said accessory pattern includes alignment marks in an upper layer wiring process.
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    同族专利:
    公开号 | 公开日
    KR100368569B1|2003-07-10|
    JPH11121327A|1999-04-30|
    US6369456B1|2002-04-09|
    CN1154169C|2004-06-16|
    CN1214541A|1999-04-21|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-10-09|Priority to JP9-276886
    1997-10-09|Priority to JP9276886A
    1998-10-01|Application filed by 가네꼬 히사시, 닛본 덴기 가부시끼가이샤
    1999-05-25|Publication of KR19990036785A
    2003-07-10|Application granted
    2003-07-10|Publication of KR100368569B1
    优先权:
    申请号 | 申请日 | 专利标题
    JP9-276886|1997-10-09|
    JP9276886A|JPH11121327A|1997-10-09|1997-10-09|Semiconductor device and its manufacture|
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